Cypress Semiconductor /psoc63 /SMIF0 /INTR

Activated in MMIO mode, when a TX data FIFO trigger ‘tr_tx_req’ is activated.

Activated in MMIO mode, when a RX data FIFO trigger ‘tr_rx_req’ is activated.

Activated in XIP mode, if:

• The selected device’s ADDR_CTL.DIV2 is ‘1’ and the AHB-Lite bus transfer address is not a multiple of 2.
• The selected device’s ADDR_CTL.DIV2 is ‘1’ and the XIP transfer request is NOT for a multiple of 2 Bytes.

Note: In dual-quad SPI mode (ADDR_CTL.DIV is ‘1’), each memory device contributes a 4-bit nibble for read data or write data. This is only possible if the request address is a multiple of 2 and the number of requested Bytes is a multiple of 2.

Activated in MMIO mode, on an AHB-Lite write transfer to the TX command FIFO (TX_CMD_FIFO_WR) with not enough free entries available.

Activated in MMIO mode, on an AHB-Lite write transfer to the TX data FIFO (TX_DATA_FIFO_WR1, TX_DATA_FIFO_WR2, TX_DATA_FIFO_WR4) with not enough free entries available.

Activated in MMIO mode, on an AHB-Lite read transfer from the RX data FIFO (RX_DATA_FIFO_RD1, RX_DATA_FIFO_RD2, RX_DATA_FIFO_RD4) with not enough entries available. Only activated for NON test bus controller transfers.